Logic analyzers in use today function by observing multiple channels' incoming digital data and performing a data storage function based upon bit patterns identified in the incoming data. The intelligence of the logic analyzer lies in its sequencer, which observes the incoming data signals, and produces signaling based upon the incoming data patterns. The signaling is typically a set of output signals that direct other areas of the logic analyzer to perform functions. A user is able to designate those functions performed and what input patterns cause the designated functions to be performed. The sequencer of the logic analyzer is a programmable state machine that makes decisions based upon patterns in the incoming data. One method of implementing a state machine is to provide a look up table (herein “LUT”). As such, the LUT accepts a current state of the sequencer and the incoming data as inputs that provides output indicating a new state of the sequencer and signaling destined to initiate performance of designated functions. Ideally, the sequencer operates at the speed of the incoming data. As data speeds and number of channels increase, however, it becomes more difficult to provide a sequencer fast enough to accommodate the incoming data.
One method for addressing the data speed challenge is to de-multiplex the incoming data to a more manageable speed for the LUT. For each de-multiplex factor, however, memory requirements to implement the sequencer increase geometrically and the solution quickly becomes prohibitively costly. Additionally, it takes more time to process de-multiplexed data through the sequencer and at some point, the benefits gained through de-multiplexing are lost due to increased processing time. Another method is to cascade the LUTs to reduce the memory requirements. Disadvantageously, however, each LUT and interconnecting logic must still operate at the speed of the incoming data. Incoming digital data speeds are currently at 2 GHz and increasing. Using current technology, cascaded LUTs are not able to operate at that speed.
There is a need, therefore, to provide a sequencer that can operate at speed for incoming digital data with an opportunity for improved speeds as technology progresses.